library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

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entity Pixel_column is
    port(
         c_data_in: in std_logic_vector(7 downto 0);
         c_shift: in std_logic;
         c_clock: in std_logic;

         data_out_row1, data_out_row2, data_out_row3: out std_logic_vector(7 downto 0)
    );
end Pixel_column;

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architecture struc of Pixel_column is

    signal pixel_1_2: std_logic_vector(7 downto 0);
    signal pixel_2_3: std_logic_vector(7 downto 0);
     
    component Pixel is
        port(
             data_in: in std_logic_vector(7 downto 0);
               shift: in std_logic;
               clock: in std_logic;

            data_out: out std_logic_vector(7 downto 0)
        );
    end component;

begin

    pixel1: Pixel port map (data_in   => c_data_in, 
                            shift     => c_shift,
                            clock     => c_clock,
                            data_out  => pixel_1_2);

    pixel2: Pixel port map (data_in   => pixel_1_2, 
                            shift     => c_shift,
                            clock     => c_clock,
                            data_out  => pixel_2_3);
   
    pixel3: Pixel port map (data_in   => pixel_2_3, 
                            shift     => c_shift,
                            clock     => c_clock,
                            data_out  => data_out_row3);

   data_out_row1 <= pixel_1_2;
   data_out_row2 <= pixel_2_3;

end struc;

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