--
-- Author: Chad Nelson
-- Date: 2/29/2012
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library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

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entity Pixel is
    port(
         data_in: in std_logic_vector(7 downto 0);
           shift: in std_logic;
           clock: in std_logic;

        data_out: out std_logic_vector(7 downto 0)
    );
end Pixel;

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architecture behv of Pixel is

    signal tmp: std_logic_vector(7 downto 0);

begin

    process (data_in, clock, shift) begin

        -- If rising edge of clock and shift is '1'
        if (clock = '1' and clock'event and shift = '1') then
            tmp <= data_in;
        end if;

    end process;

    data_out <= tmp;

end behv;

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