--
-- Author: Chad Nelson
-- Date: 2/29/2012
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library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

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entity Controller is
    port(
                 aeId: in std_logic_vector(1 downto 0);
    base_load_address: in std_logic_vector(47 downto 0); -- AEG[0]
   base_store_address: in std_logic_vector(47 downto 0); -- AEG[1]
                 rows: in std_logic_vector(63 downto 0); -- AEG[2]
              columns: in std_logic_vector(63 downto 0); -- AEG[3]
                shift: in std_logic; -- '1' if all MC loading data have valid data; '0' otherwise
                reset: in std_logic;
                clock: in std_logic;
                 idle: in std_logic;
                start: in std_logic;

         load_address: out std_logic_vector(47 downto 0);
        store_address: out std_logic_vector(47 downto 0);
          store_valid: out std_logic; -- will be '0' until first three rows are loaded
                 done: out std_logic; -- '1' after last shift occurs
    );
end Controller;

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architecture behv of Controller is

    -- TODO signal definitions

begin

    -- TODO architecture

end behv;

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