library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

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entity BigShifter is
    port(
         mc_data_in: in std_logic_vector(63 downto 0);
         mc_shift: in std_logic;
         mc_clock: in std_logic;

         c1_data_out_row1, c1_data_out_row2, c1_data_out_row3: out std_logic_vector(7 downto 0);
         c2_data_out_row1, c2_data_out_row2, c2_data_out_row3: out std_logic_vector(7 downto 0);
         c3_data_out_row1, c3_data_out_row2, c3_data_out_row3: out std_logic_vector(7 downto 0);
         c4_data_out_row1, c4_data_out_row2, c4_data_out_row3: out std_logic_vector(7 downto 0);
         c5_data_out_row1, c5_data_out_row2, c5_data_out_row3: out std_logic_vector(7 downto 0);
         c6_data_out_row1, c6_data_out_row2, c6_data_out_row3: out std_logic_vector(7 downto 0);
         c7_data_out_row1, c7_data_out_row2, c7_data_out_row3: out std_logic_vector(7 downto 0);
         c8_data_out_row1, c8_data_out_row2, c8_data_out_row3: out std_logic_vector(7 downto 0)
    );
end BigShifter;

architecture struc of BigShifter is

component Pixel_column is
    port(
         c_data_in: in std_logic_vector(7 downto 0);
         c_shift: in std_logic;
         c_clock: in std_logic;

         data_out_row1, data_out_row2, data_out_row3: out std_logic_vector(7 downto 0)
    );
end component;
  
begin

    column1: Pixel_column port map (c_data_in      => mc_data_in(7 downto 0), 
                                    c_shift        => mc_shift,
                                    c_clock        => mc_clock,
                                    data_out_row1  => c1_data_out_row1, 
                                    data_out_row2  => c1_data_out_row2, 
                                    data_out_row3  => c1_data_out_row3);

    column2: Pixel_column port map (c_data_in      => mc_data_in(15 downto 8), 
                                    c_shift        => mc_shift,
                                    c_clock        => mc_clock,
                                    data_out_row1  => c2_data_out_row1, 
                                    data_out_row2  => c2_data_out_row2, 
                                    data_out_row3  => c2_data_out_row3);

    column3: Pixel_column port map (c_data_in      => mc_data_in(23 downto 16), 
                                    c_shift        => mc_shift,
                                    c_clock        => mc_clock,
                                    data_out_row1  => c3_data_out_row1, 
                                    data_out_row2  => c3_data_out_row2, 
                                    data_out_row3  => c3_data_out_row3);

    column4: Pixel_column port map (c_data_in      => mc_data_in(31 downto 24), 
                                    c_shift        => mc_shift,
                                    c_clock        => mc_clock,
                                    data_out_row1  => c4_data_out_row1, 
                                    data_out_row2  => c4_data_out_row2, 
                                    data_out_row3  => c4_data_out_row3);

    column5: Pixel_column port map (c_data_in      => mc_data_in(39 downto 32), 
                                    c_shift        => mc_shift,
                                    c_clock        => mc_clock,
                                    data_out_row1  => c5_data_out_row1, 
                                    data_out_row2  => c5_data_out_row2, 
                                    data_out_row3  => c5_data_out_row3);

    column6: Pixel_column port map (c_data_in      => mc_data_in(47 downto 40), 
                                    c_shift        => mc_shift,
                                    c_clock        => mc_clock,
                                    data_out_row1  => c6_data_out_row1, 
                                    data_out_row2  => c6_data_out_row2, 
                                    data_out_row3  => c6_data_out_row3);
 
    column7: Pixel_column port map (c_data_in      => mc_data_in(55 downto 48), 
                                    c_shift        => mc_shift,
                                    c_clock        => mc_clock,
                                    data_out_row1  => c7_data_out_row1, 
                                    data_out_row2  => c7_data_out_row2, 
                                    data_out_row3  => c7_data_out_row3);

    column8: Pixel_column port map (c_data_in      => mc_data_in(63 downto 56), 
                                    c_shift        => mc_shift,
                                    c_clock        => mc_clock,
                                    data_out_row1  => c8_data_out_row1, 
                                    data_out_row2  => c8_data_out_row2, 
                                    data_out_row3  => c8_data_out_row3);
end struc;

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